1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor structure, and particularly to a method of fabricating a semiconductor structure during which rounding problem of an epitaxial layer can be avoided or reduced.
2. Description of the Prior Art
As the semiconductor processes advance to very deep sub micron era such as 65-nm node, even 28 nm or beyond, how to increase the driving current for MOS transistors has become a critical issue. In order to improve device performance, strained-silicon technology has been developed. Putting a strain on a semiconductor crystal alters the speed at which charges move through that crystal. Strain makes MOS transistors work better by enabling electrical charges, such as electrons, to pass more easily through the silicon lattice of the gate channel.
One of the methods to put a strain on the silicon lattice of the gate channel is that combining a selective epitaxial growth (SEG) technology. Recesses are formed in the substrate beside the gate structure and then an epitaxial layer, such as silicon germanium (SiGe) layer having a crystal lattice arrangement the same as that of the substrate is formed within the recesses through the epitaxial growth process to serve as a source/drain, so as to apply a stress to the crystal lattice of the gate channel.
FIG. 1 is a schematic, cross-sectional view illustrating a conventional semiconductor structure. As shown in FIG. 1, in the semiconductor structure 10, a gate structure 14 is formed on a substrate 12. The gate structure 14 includes a gate dielectric 14a, a gate electrode 14b, and a spacer 14c. Two recesses 16 (the dotted line) are formed in the substrate 12 adjacent to two sides of the gate structure 14. An epitaxial layer 18 is formed within the recesses 16 to serve as a source/drain region. Thereafter, a metal silicide layer 20 is formed on each up surface of the source/drain region and the gate structure 14. However, the resultant shape of the epitaxial layer 18 often becomes round without straight sides and it deviates very much from the original shape of the recess 16. In such result, the length of the gate channel 22 between the two recesses 16 under the gate structure 14 becomes longer than a predetermined one, and the stress effect of the epitaxial layer 18 to the gate channel 22 is reduced.
Therefore, there is still a need for a novel method of fabricating a semiconductor structure to solve the aforesaid issue.